1. Field of the Invention
The present invention relates to an embedded system, and more particularly, to a bridge for interfacing buses within the embedded system.
2. Description of the Related Art
FIG. 1 is a configuration diagram showing an embedded system conforming to a conventional Advanced Microcontroller Bus Architecture (AMBA) standard.
The embedded system conforming to the conventional AMBA comprises an AHB (Advanced High-Performance Bus)-to-APB (Advanced Peripheral Bus) bridge 1, an AHB 2, an APB 3, a central processing unit (CPU) 11, an AHB master_1 12, an AHB master_2 13, an AHB master_3 14, an AHB slave_1 15, an AHB slave_2 16, a light emitting diode (LED) 17, a local area network (LAN) 18, and a universal asynchronous receiver/transmitter (UART) 19.
AMBA refers to a standard for an on-chip bus, which is provided by ARM (Advanced RISC Machines) Ltd., and is widely used in an embedded system owing to the simple structure and the low power consumption. Since various peripheral devices connected to outside of a chip conforming to the AMBA standard operate at speeds lower than the clock speed of the CPU 11, the AMBA standard has two bus layers, which are the AHB 2 and the APB 3. The CPU 11 and the devices 12, 13, 14, 15, and 16 operating at the clock speed of the CPU 11 are connected to the AHB. The peripheral devices 17, 18, and 19 operating at speeds lower than the clock speed of the CPU 11 are connected to the APB 3. FIG. 1 illustrates the LED 17, the LAN 18, and the UART 19 as the peripheral devices 17, 18, and 19.
The AHB-to-APB bridge 1 is located between the AHB 2 and the APB 3, and interfaces the AHB 2 and the APB 3 operating at different speeds. If the CPU 11 transmits a certain signal to any one of the peripheral devices 17, 18, and 19, e.g., the UART 19, without the AHB-to-APB bridge 1, the signal transmitted from the CPU 11 will disappear before the UART 19 reads the signal because of a mismatch of operating timings.
The peripheral devices 17, 18, and 19 that are connected to the APB 3 operate at various speeds.
According to the conventional AMBA standard, the APB 3 should operate depending on the peripheral device operating at the lowest speed among the peripheral devices 17, 18, and 19, or a wrapper, which serves as a speed compensation circuit, should be added to each of the peripheral devices 17, 18, and 19, as shown in FIG. 1, while the APB 3 remains the same speed.
For instance, in an embedded system equipped with the AHB-to-APB bridge 1 designed under the assumption that the AHB 2 operates at 100 MHz and the APB 3 operates at 20 MHz, there may occur a case where the LAN 18 and the UART 19 operate at 20 MHz but the LED 17 operates at a speed lower than 20 MHz. In this case, the APB 3 should operate at a speed lower than 20 MHz to match the speed of the LED 17, or a wrapper, a speed compensation circuit, should be added to the LED 17.
There is a problem in that operating the APB 3 depending on a peripheral device operating at the lowest speed among the peripheral devices 17, 18, and 19 significantly degrades the overall processing speed of the embedded system, i.e., the performance of the embedded system. In addition, there is a problem in that adding a wrapper, a speed compensation circuit, to each of the peripheral devices 17, 18, and 19 results in the performance degradation, power consumption increase, or resource waste.